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Preliminary Technical Data
FEATURES
Specified for VDD of 2.35 V to 5.25 V Low Power: 6 mW max at 625 kSPS with 3V Supplies 12 mW max at 625 kSPS with 5V Supplies 4 Analog Input Channels with a Sequencer Software Configurable Analog Inputs: 4-Channel Single Ended Inputs 2-Channel Fully Differential Inputs 2-Channel Pseudo Differential Inputs Accurate On-chip 2.5 V Reference Wide Input Bandwidth: 70dB SNR at 50kHz Input Frequency No Pipeline Delays High Speed Parallel Interface - Word/Byte Modes Full Shutdown Mode: 1A max 28 Lead TSSOP Package
4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer AD7934-6
The AD7934-6 has an accurate on-chip 2.5 V reference that can be used as the reference source for the analog to digital conversion. Alternatively, this pin can be overdriven to provide an external reference. This part uses advanced design techniques to achieve very low power dissipation at high throughput rates. It also features flexible power management options. An on-chip Control register allows the user to set up different operating conditions including analog input range and configuration, output coding, power management and channel sequencing.
GENERAL DESCRIPTION
The AD7934-6 is a 12-bit, high speed, low power, successive approximation (SAR) ADC. It operates from a single 2.35 V to 5.25 V power supply and features throughput rates up to 625 kSPS. The AD7934-6 contains a low noise, wide bandwidth, differential track/hold amplifier that can handle input frequencies up to 3.5MHz. The AD7934-6 features 4 analog input channels with a channel sequencer to allow a consecutive sequence of channels to be converted on. It can accept either Single-ended, Fully Differential or Pseudo Differential analog inputs. The conversion process and data acquisition are controlled using standard control inputs allowing easy interfacing to Microprocessors and DSPs. The input signal is sampled on the falling edge of CONVST and the conversion is also initiated at this point.
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
1. 2. 3. 4. High Throughput with Low Power Consumption. Four Analog Inputs with a Channel Sequencer. Accurate on-chip 2.5 V reference. Software Configurable Analog Inputs. Single-Ended, Pseudo Differential or Fully Differential analog inputs that are software selectable. Single-supply Operation with VDRIVE Function. The VDRIVE function allows the parallel interface to connect directly to 1.8 V, 3V or 5 V processor systems independent of VDD. No Pipeline Delay. Accurate control of the sampling instance via a CONVST input and once off conversion control.
5.
6. 7.
Rev. PrB
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AD7934-6
TABLE OF CONTENTS
Features .......................................................................................... 1 General Description..................................................................... 1 Product Highlights ....................................................................... 1 Specifications..................................................................................... 3 AD7934-6-6 Specifications......................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings ....................................................... 7 Pin Function Description ................................................................ 8 PIN CONFIGURATION............................................................. 8 Terminology .................................................................................... 10 Typical Performance Characteristics AD7934-6 ........................ 12 Circuit Information ........................................................................ 16 Converter Operation.................................................................. 16 ADC Transfer Function............................................................. 16
Preliminary Technical Data
Typical Connection Diagram ................................................... 17 Analog Input Structure.............................................................. 17 The Analog Inputs...................................................................... 18 Analog Input Selection .............................................................. 20 Reference Section ....................................................................... 21 Parallel Interface......................................................................... 22 power Modes Of Operation...................................................... 23 Power vs. Throughput rate ........................................................ 23 Microprocessor Interfacing....................................................... 23 Application Hints ........................................................................... 26 Grounding and Layout .............................................................. 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
Revision PrB: Initial Version
Rev. PrB | Page 2 of 27
Preliminary Technical Data SPECIFICATIONS
AD7934-6 SPECIFICATIONS
AD7934-6
VDD = VDRIVE=2.35 V to 5.25V, Internal/External VREF = 2.5V, FCLKIN = 10MHz, FSAMPLE = 625 kSPS; TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion2 (SINAD) Signal to Noise Ratio (SNR) 2 Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay 2 Aperture Jitter 2 Full Power Bandwidth2, 3 DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Total Unadjusted Error Single Ended & Pseudo Differential Input Offset Error2 Offset Error Match 2 Gain Error 2 Gain Error Match 2 Fully Differential Input Positive Gain Error 2 Positive Gain Error Match 2 Zero Code Error 2 Zero Code Error Match 2 Negative Gain Error 2 Negative Gain Error Match 2 ANALOG INPUT Single Ended Input Range Pseudo Differential Input Range: VIN+ VINFully Differential Input Range: VIN+ and VINVIN+ and VINDC Leakage Current 4 Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage B Version1 70 70 -75 -75 -85 -85 5 50 20 2.5 12 1 0.95 TBD 4.5 0.5 2 0.6 2 0.6 3 1 1 0.5 0 to VREF or 0 to 2 x VREF 0 to VREF or 2 x VREF -0.1 to 0.4 VCM VREF/2 VCM VREF 1 45/10 2.55 Units dB min dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max Twos Complement Output Coding LSB max LSB max LSB max LSB max LSB max LSB max V V V V V A max pF typ V Depending on RANGE bit in the control register Depending on RANGE bit in the control register VCM = Common Mode Voltage = VREF/2 Only when VDD = 4.75 V to 5.25 V. VCM = VREF When in Track/Hold 1% Specified Performance Test Conditions/Comments FIN=50kHz Sine Wave
-80dB typ -82dB typ fa = 40.1kHz, fb = 51.5kHz
@ 3 dB @ 0.1 dB
Guaranteed No Missed Codes to 12 Bits. Straight Binary Output Coding
1 2
Temperature ranges as follows: B Versions: -40C to +85C. See Terminology Section. 3 Analog inputs with slew rates exceeding 27V/s (full-scale input sine wave > 3.5MHz) within the acquisition time may cause an incorrect result to be returned by the converter 4 Guaranteed by characterization 5 This device is operational with an external reference in the range 0.1 V to 3.5 V in differential mode and 0.1V to VDD in pseudo differential and single ended modes. See the Reference Section for more information.
Rev. PrB | Page 3 of 27
AD7934-6
Parameter VREF Input Voltage DC Leakage Current VREF Input Impedance VREFOUT Output Voltage VREFOUT Tempco VREF Noise VREF Output Impedance VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD 6 Normal Mode(Static) Normal Mode (Operational) Auto StandBy Mode Auto Shutdown Mode Full Shut-Down Mode Power Dissipation Normal Mode (Operational) Auto Standby-Mode (Static) Auto Shutdown-Mode (Static) Full Shutdown-Mode
6
Preliminary Technical Data
B Version1 VDD 1 10 2.5 15 10 130 10 15/25 2.4 0.8 x VDRIVE 0.8 0.2 x VDRIVE 1 10 Units V A max k typ V ppm/C typ V typ V typ typ pF typ V min V min V max V max A max pF max Test Conditions/Comments VDD < 2.7 V
0.1% @ 25C 0.1Hz to 10Hz Bandwidth 0.1Hz to 1MHz Bandwidth When in Track/hold VDRIVE = 2.7 V to 5.25 V VDRIVE < 2.7V VDRIVE = 2.7 V to 5.25 V VDRIVE < 2.7V Typically 10 nA, VIN = 0 V or VDRIVE
2.4 V min VDRIVE - 0.2 V min 0.4 V max 10 A max 10 pF max Straight (Natural) Binary 2s Complement t2 + 13 tclk + t20 350 625 2.35/5.25 3.6 /5.25 1.6/3.6 0.5 2.4 2 1.55 90 1 1 1 12 6 450 270 5 3 5/3 ns ns max kSPS max V min/max V min/max V min/max mA typ mA max mA max mA typ A max mA typ A max A max mW max mW max W max W max W max W max W max
ISOURCE= 200 A; VDRIVE= 2.7 V to 5.25 V ISOURCE= 200 A; VDRIVE < 2.7 V ISINK=200A
CODING bit in the control register set to 0. CODING bit in the control register set to 1.
Full Scale Step input.
VDD = 3.6 V to 5.25 V VDD = 2.7 V to 3.6 V Digital I/Ps = 0V or VDRIVE. VDD= 2.7V to 5.25V. SCLK on or off. VDD= 4.75V to 5.25V. VDD= 2.7V to 3.6V. Fsample = 100kSPS (Static) Fsample = 100kSPS (Static) SCLK On or Off. VDD= 5V. VDD= 3V. VDD= 5V. VDD= 3V. VDD= 5V. VDD= 3V. VDD= 5V / 3V.
Measured with a midscale dc input.
Rev. PrB | Page 4 of 27
Preliminary Technical Data
TIMING SPECIFICATIONS1
AD7934-6
(VDD = VDRIVE=2.35 V to 5.25V, Internal/External VREF = 2.5V, FCLKIN = 10MHz, FSAMPLE = 625kSPS; TA = TMIN to TMAX, unless otherwise noted.) Table 2.
Parameter fCLKIN2 tquiet t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 3 t14 4 t15 t16 t17 t18 t19 t20 Limit at TMIN, TMAX AD7934-6 Units 10 kHz min 20 MHz max 10 10 20 Tbd 0 0 25 10 5 1/2 tCLKIN 0 0 55 50 5 40 15 5 10 0 5 Tbd ns min ns min ns min ns min ns min ns max ns min ns min ns min ns min ns min ns max ns min ns max ns min ns max ns min ns min ns min ns min ns max ns min Description
Minimum time between conversions (i.e. time from when the data bus goes into three-state until the next falling edge of CONVST) CONVST pulsewidth CONVST falling edge to CLKIN falling edge setup time CLKIN falling edge to BUSY rising edge CS to WR setup time CS to WR hold time WR Pulse Width Data Setup time before WR Data Hold after WR New data valid before falling edge of BUSY CS to RD setup time CS to RD hold time RD Pulse Width Data access time after RD Bus relinquish time after RD Bus relinquish time after RD HBEN to RD setup time HBEN to RD hold time Minimum time between Reads/Writes HBEN to WR setup time HBEN to WR hold time CLKIN falling edge to BUSY rising edge
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. All timing specifications given above are with a 25pF load capacitance. See Figure 2, Figure 3, Figure 4 and Figure 5. 2 Mark/Space ratio for CLKIN is 40/60 to 60/40. 3 The time required for the output to cross TBD. 4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t14 quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
1
Rev. PrB | Page 5 of 27
AD7934-6
Preliminary Technical Data
Figure 2. AD7934-6 Parallel Interface - Write Cycle timing for Word Mode Operation (W/B = 1)
Figure 3. AD7934-6 Parallel Interface - Write Cycle Timing for Byte Mode Operation (W/B = 0)
Figure 4. AD7934-6 Parallel Interface - Conversion and Read Cycle in Word Mode (W/B = 1)
Rev. PrB | Page 6 of 27
Preliminary Technical Data
AD7934-6
Figure 5. AD7934-6 Parallel Interface - Read Cycle Timing for Byte Mode Operation (W/B = 0)
ABSOLUTE MAXIMUM RATINGS
(TA = +25C unless otherwise noted) Table 3.
Parameter VDD to AGND/DGND VDRIVE to AGND/DGND Analog Input Voltage to AGND Digital Input Voltage to DGND VDRIVE to VDD Digital Output Voltage to AGND VREFIN to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 secs) Infared (15 secs) ESD
1
Rating -0.3 V to 7 V -0.3 V to 7 V -0.3 V to VDD + 0.3 V -0.3 V to 7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V 10 mA -40C to +85C -65C to +150C +150C 97.9C/W (TSSOP) 14C/W (TSSOP) +215C +220C 2kV
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Transient currents of up to 100 mA will not cause SCR latch up.
ESD Caution
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 7 of 27
AD7934-6 PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
Preliminary Technical Data
Figure 6. Pin Configuration
Table 4. Pin Configuration
Pin no. 1 2 Pin Mnemonic VDD W/B Function Power Supply Input. The VDD range for the AD7934-6 is from +2.35 V to +5.25 V. The supply should be decoupled to AGND with a 0.1F capacitor and a 10F tantalum capacitor. Word/Byte Input. When this input is logic high, data is transferred to and from the AD7934-6 in 12-bit words on pins DB0 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID is transferred on pins DB0 to DB7 and pin DB8/HBEN assumes its HBEN functionality. Data Bits 0 to 7. Three state parallel digital I/O pins that provide the conversion result and also allows the Control register to be programmed. These pins are controlled by CS, RD and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7934-6 will operate. Digital Ground. This is the ground reference point for all digital circuitry on the AD7934-6. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three state I/O pin that is controlled by CS, RD and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7934-6 is on DB0 to DB7. When HBEN is high, the top 4 bits of the data being written to or read from the AD7934-6 are on DB0 to DB3. When reading from the device, DB4 of the high byte will always be zero and DB5 and DB6 will contain the ID of the channel for which the conversion result corresponds (See Channel Address Bits in Table 7). When writing to the device, DB4 to DB7 of the high byte must be all zeros. Data Bits 9 to 11. Three state parallel digital I/O pins that provide the conversion result and also allows the Control register to be programmed in Word Mode. These pins are controlled by CS, RD and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output will go low. The track/hold returns to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY goes low. Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7934-6 takes 13.5 clock cycles. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track/hold goes from track to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following powerdown, when operating in the Auto-shutdown or Auto Standby mode, a rising edge on CONVST is used to power up the device.
Rev. PrB | Page 8 of 27
3-10
DB0 to DB7
11 12 13
VDRIVE DGND DB8/HBEN
14-16
DB9 to DB11
17
BUSY
18
CLKIN
19
CONVST
Preliminary Technical Data
Pin no. 20 21 22 23 Pin Mnemonic WR RD CS AGND Function
AD7934-6
24
VREFIN/VREFOUT
25-28
VIN 0 - VIN 3
Write Input. Active low logic input used in conjunction with CS to write data to the Control register. Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. Chip Select. Active low logic input used in conjunction with RD and WR to Read conversion data or to Write data to the Control register. Analog Ground. This is the ground reference point for all analog circuitry on the AD7934-6. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to 3.5 V for differential mode and is 0.1 V to VDD in single ended and pseudo differential mode, depending on VDD. Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track/hold. The analog inputs can be programmed to be four single ended inputs, two fully differential pairs or two pseudo differential pairs by setting the MODE bits in the Control register appropriately (see Table 7). The analog input channel to be converted can either be selected by writing to the Address bits (ADD1 and ADD0) in the control register prior to the conversion, or the on-chip sequencer can be used. The input range for all input channels can either be 0 V to VREF or 0 V to 2 x VREF and the coding can be binary or two's complement, depending on the states of the RANGE and CODING bits in the Control register. Any unsed input channels should be connected to AGND to avoid noise pickup.
Rev. PrB | Page 9 of 27
AD7934-6
TERMINOLOGY
Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . .000) to (00 . . . 001) from the ideal, i.e. AGND + 1 LSB Offset Error Match This is the difference in offset error between any two channels. Gain Error This is the deviation of the last code transition (111 . . .110) to (111 . . . 111) from the ideal (i.e., VREF - 1 LSB) after the offset error has been adjusted out. Gain Error Match This is the difference in Gain error between any two channels. Zero Code Error This applies when using the 2's complement output coding option, in particular to the 2 x VREF input range with -VREF to +VREF biased about the VREFIN point. It is the deviation of the mid scale transition (all 0s to all 1s) from the ideal VIN voltage, i.e. VREF - 1 LSB. Zero Code Error Match This is the difference in Zero Code Error between any two channels. Positive Gain Error This applies when using the 2's complement output coding option, in particular to the 2 x VREF input range with -VREF to +VREF biased about the VREFIN point. It is the deviation of the last code transition (011. . .110) to (011 .. . 111) from the ideal (i.e., +VREF - 1 LSB) after the Zero Code Error has been adjusted out. Positive Gain Error Match This is the difference in Positive Gain Error between any two channels.
Preliminary Technical Data
Negative Gain Error This applies when using the 2's complement output coding option, in particular to the 2 x VREF input range with - VREF to +VREF biased about the VREF point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., - VREFIN + 1 LSB) after the Zero Code Error has been adjusted out. Negative Gain Error Match This is the difference in Negative Gain Error between any two channels. Channel-to-Channel Isolation Channel-to-Channel Isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale sine wave signal to all 3 nonselected input channels and applying a 50kHz signal to the selected channel. The channel to channel isolation is defined as the ratio of the power of the 50kHz signal on the selected channel, to the power of the noise signal that appears in the FFT of this channel. PSRR (Power Supply Rejection Ratio) The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100mV p-p sine wave applied to the ADC VDD supply of frequency fs. The frequency of the input varies from 1kHz to 1MHz. PSRR (dB) = 10log(Pf/Pfs) Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output. Track/Hold Acquisition Time The track/hold amplifier returns into track mode and the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion. Signal to (Noise + Distortion) Ratio (SINAD) This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fs/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB.
Rev. PrB | Page 10 of 27
Preliminary Technical Data
Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7934-6, it is defined as: Intermodulation Distortion
AD7934-6
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7934-6 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.
THD(dB ) = -20 log
V2 + V3 + V4 + V5 + V6 V1
2
2
2
2
2
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak
Rev. PrB | Page 11 of 27
AD7934-6 TYPICAL PERFORMANCE CHARACTERISTICS
PERFORMANCE CURVES
Ta = 25C, unless otherwise noted
Preliminary Technical Data
Figure 7. PSRR versus Supply ripple Frequency without supply decoupling
Figure 11. AD7934-6 Typical DNL @ VDD=5V
Figure 8. Channel to Channel Isolation
Figure 12. AD7934-6 Typical INL @ VDD=5V
Figure 9. AD7934-6 SINAD vs Analog Input Frequency for various Supply Voltages
Figure 13. AD7934-6 Change in INL vs VREF for VDD=5V
Figure 10. AD7934-6 FFT @ VDD=5V
Figure 14.AD7934-6 Change in DNL vs VREF for VDD=5V
Rev. PrB | Page 12 of 27
Preliminary Technical Data
AD7934-6
Figure 15. AD7934-6 Change in ENOB vs VREF for VDD=5V
Figure 16. AD7934-6 Offset vs VREF
Figure 17. AD7934-6 Histogram of codes @ VDD=5V with the Internal Reference
Figure 18. AD7934-6 Histogram of codes @ VDD=5V with an External Reference
Rev. PrB | Page 13 of 27
AD7934-6
CONTROL REGISTER
Preliminary Technical Data
The Control Register on the AD7934-6 is a 12-bit, write-only register. Data is written to this register using the CS and WR pins. The Control Register is shown below and the functions of the bits are described in Table 5. At power up, the default bit settings in the Control Register are all 0s.
Figure 19. Control Register Bits.
Table 5. Control Register Bit Function Description
Bit 11, 10 9 8 7 6, 5 4,3 2 1 0 Mnemonic PM1, PM0 CODING REF ZERO ADD1, ADD0 MODE1, MODE0 SEQ1 SEQ0 RANGE Comment Power Management Bits. These two bits are used to select the power mode of operation. The user can choose between either normal mode or various power down modes of operation as shown in Table 6. This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding will be straight (natural) binary. If this bit is set to 1, the output coding will be twos complement. This bit selects whether the internal or an external reference is used to perform the conversion. If this bit is logic 0, an external reference should be applied to the VREF pin and if it is 1, the internal reference is selected (see the Reference Section). This bit is not used so should always be set to logic 0. These two address bits are used to either select which analog input channel is to be converted on in the next conversion if the sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being used as described in Table 8. The selected input channel is decoded as shown in Table 7. The two Mode pins select the type of analog input on the four VIN pins. The AD7934-6 can have either 4 Single Ended inputs, 2 Fully Differential inputs or 2 Pseudo Differential inputs. See Table 7. The SEQ1 bit in the Control register is used in conjunction with the SEQ0 bit to control the sequencer function. See Table 8. The SEQ0 bit in the Control register is used in conjunction with the SEQ1 bit to control the sequencer function. See Table 8. This bit selects the analog input range of the AD7934-6. If it is set to 0 then the analog input range will extend from 0V to VREF. If it is set to 1 then the analog input range will extend from 0V to 2xVREF. When this range is selected, AVDD must be 4.75 V to 5.25 V.
Table 6. Power Mode Selection using the Power Management Bits in the Control Register
PM1 0 0 1 1 PM0 0 1 0 1 Mode Normal Mode Auto Shutdown Auto Standby Full Shutdown Description When operating in Normal Mode, all circuitry is fully powerered up at all times. When operating in Auto Shutdown mode, the AD7934-6 will enter Full Shutdown mode at the end of each conversion. In this mode, all circuitry is powered down. When the AD7934-6 enter this mode, all circuitry is partially powered down. This mode is similar to Auto Shutdown but allows the part to power up in 1sec. When the AD7934-6 enters this mode, all circuitry is powered down. The information in the Control Register is retained.
Table 7. Analog Input Type Selection
Rev. PrB | Page 14 of 27
Preliminary Technical Data
Channel Address MODE0=0, MODE1=0 4 Single-Ended I/P Channels VIN+ VINVIN0 AGND VIN1 AGND VIN2 AGND VIN3 AGND MODE0=0, MODE1=1 2 Fully Differential I/P Channels VIN+ VINVIN0 VIN1 VIN1 VIN0 VIN2 VIN3 VIN3 VIN2 MODE0=1, MODE1=0 2 Pseudo Differential I/P Channels VIN+ VINVIN0 VIN1 VIN1 VIN0 VIN2 VIN3 VIN3 VIN2
AD7934-6
MODE0=1, MODE1=1 NOT USED
ADD1 0 0 1 1
ADD0 0 1 0 1
SEQUENCER OPERATION
The configuration of the SEQ0 and SEQ1 bits in the control register allow the user use the sequencer function. Table 8 outlines the two modes of operation of the Sequencer. Table 8. Sequence Selection
SEQ0 0 0 1 1 SEQ1 0 1 0 1 Sequence Type This configuration is selected when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of the channel address bits ADD1 and ADD0 in each prior write operation. This mode of operation reflects the normal operation of a multi-channel ADC, without the Sequencer function being used, where each write to the AD7934-6 selects the next channel for conversion. NOT USED NOT USED This configuration is used in conjunction with the Channel Address bits (ADD1 and ADD0) to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by the Channel Address bits in the Control Register. When operating in Differential or Pseudo Differential mode, the ADC will not convert on inverse pairs ( e.g. VIN1 and VIN0)
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AD7934-6 CIRCUIT INFORMATION
The AD7934-6 is a 4 channel, 12-bit, single supply, successive approximation Analog to Digital converter. It can be operated from a either a 2.35 V to 3.6 V or a 4.75 V to 5.25 V power supply and features throughput rates up to 625kSPS. The AD7934-6 provides the user with an on-chip track/hold, an internal accurate reference, an analog to digital converter, and a parallel interface housed in a 28-Lead TSSOP package. The AD7934-6 has four analog input channels which can be configured to be 4 single ended inputs, 2 fully differential pairs or 2 pseudo differential pairs. There is an on-chip channel sequencer which allows the user to select a consecutive sequence of channels through which the ADC can cycle with each falling edge of CONVST. The analog input range for the AD7934-6 is 0 to VREF or 0 to 2 x VREF depending on the status of the RANGE bit in the Control register. The output coding of the ADC can be either Binary or Twos complement, depending on the status of the CODING bit in the Control register.
Preliminary Technical Data
comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The Control Logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC's output code. The output impedances of the sources driving the VIN+ and the VIN- pins must be matched otherwise the two inputs will have different settling times, resulting in errors.
Figure 21. ADC Conversion Phase
The AD7934-6 provides flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the power management bits, PM1 and PM0, in the Control Register.
ADC TRANSFER FUNCTION
The output coding for the AD7934-6 is either straight binary or two's complement, depending on the status of the CODING bit in the control register. The designed code transitions occur at successive LSB values (i.e. 1LSB, 2LSBs, etc.) and the LSB size is VREF/4096 . The ideal transfer characteristics of the AD7934-6 for both straight binary and twos complement output coding are shown in Figure 22 and Figure 23 respectively.
CONVERTER OPERATION
The AD7934-6 is a successive approximation ADC based around two capacitive DACs. Figure 20 and Figure 21 show simplified schematics of the ADC in Acquisition and Conversion phase respectively. The ADC comprises of Control Logic, a SAR and two capacitive DACs. Both figures show the operation of the ADC in Differential/Pseudo Differential Mode. Single Ended mode operation is similar but VIN- is internally tied to AGND. In acquisition phase, SW3 is closed and SW1 and SW2 are in position A, the comparator is held in a balanced condition and the sampling capacitor arrays acquire the differential signal on the input.
Figure 22. AD7934-6 Ideal Transfer Characteristic with Straight Binary Output Coding
Figure 20. ADC Acquisition Phase
When the ADC starts a conversion (Figure 21), SW3 will open and SW1 and SW2 will move to position B, causing the
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Preliminary Technical Data
ANALOG INPUT STRUCTURE
AD7934-6
Figure 25 shows the equivalent circuit of the analog input structure of the AD7934-6 in Differential/Pseudo Differential Mode. In Single Ended mode, VIN- is internally tied to AGND. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300mV. This will cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10mA without causing irreversible damage to the part. The capacitors C1, in Figure 25 are typically 4pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on-resistance of the switches. The value of these resistors is typically about 100. The capacitors, C2, are the ADC's sampling capacitors and have a capacitance of 16pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the opamp will be a function of the particular application.
Figure 23. AD7934-6 Ideal Transfer Characteristic with Twos Complement Output Coding
TYPICAL CONNECTION DIAGRAM
Figure 24 shows a typical connection diagram for the AD79346. The AGND and DGND pins are connected together at the device for good noise suppression. The VREFIN/VREFOUT pin is decoupled to AGND with a 0.47F capacitor to avoid noise pickup if the internal reference is used. Alternatively, VREFIN/VREFOUT can be connected to a external reference source and in this case the reference pin should be decoupled with a 0.1F capacitor. In both cases the analog input range can either be 0V to VREF (Range bit = 0) or 0V to 2 x VREF (Range bit = 1). The analog input configuration can be either 4 Single Ended inputs, 2 Differential Pairs or 2 Pseudo Differential Pairs (see Table 7). The VDD pin is connected to either a 3V or 5V supply. The voltage applied to the VDRIVE input controls the voltage of the digital interface and here, it is connected to the same 3V supply of the microprocessor to allow a 3V logic interface (See the digital inputs section).
Figure 25. Equivalent Analog Input Circuit. Conversion Phase -Switches Open Track Phase - Switches Closed
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of Total Harmonic Distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. Figure 26 shows a graph of the THD versus analog input signal frequency for different source impedances for both VDD = 5 V and 3 V.
Figure 24. Typical Connection Diagram
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AD7934-6
Preliminary Technical Data
Figure 28. Single Ended Mode Connection Diagram Figure 26. THD vs Analog Input Frequency for Various Source Impedances
Differential Mode The AD7934-6 can have 2 Differential Analog Input Pairs by setting the MODE0 and MODE1 bits in the control register to 0 and 1 respectively. Differential signals have some benefits over single ended signals including noise immunity based on the device's common mode rejection and improvements in distortion performance. Figure 29 defines the fully differential analog input of the AD7934-6.
Figure 27 shows a graph of THD versus analog input frequency for various supplies, while sampling at 625 kSPS with an SCLK of 10 MHz. In this case the source impedance is 10.
Figure 27. THD vs Analog Input Frequency for various Supply Voltages
THE ANALOG INPUTS
The AD7934-6 has software selectable analog input configurations. The user can choose either 4 Single Ended Inputs, 2 Fully Differential Pairs or 2 Pseudo Differential Pairs. The analog input configuration is chosen with the MODE0/MODE1 bits in the internal Control register (See Table 7). Single Ended Mode The AD7934-6 can have 4 single ended analog input channels by setting the MODE0 and MODE1 bits in the control register both to 0. In applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the ADC. The analog input range can be either 0 to VREF or 0 to 2 x VREF. If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias up this signal to make it of the correct format for the ADC. Figure 28 shows a typical connection diagram when operating the ADC in single ended mode.
Figure 29. Differential Input Definition
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins in each differential pair (i.e. VIN+ - VIN-). VIN+ and VIN- should be simultaneously driven by two signals each of amplitude VREF that are 180 out of phase. The amplitude of the differential signal is therefore -VREF to +VREF peak-to-peak (i.e. 2 x VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e. (VIN+ + VIN-)/2 and is therefore the voltage that the two inputs are centered on. This results in the span of each input being CM VREF/2. This voltage has to be set up externally and its range varies with VREF. As the value of VREF increases, the common mode range decreases. When driving the inputs with an amplifier, the actual common mode range will be determined by the amplifier's output voltage swing.
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Preliminary Technical Data
Figure 30 and Figure 31 show how the common mode range typically varies with VREF for both a 5 V and a 3 V power supply. The common mode must be in this range to guarantee the functionality of the AD7934-6. When a conversion takes place, the common mode is rejected resulting in a virtually noise free signal of amplitude -VREF to +VREF corresponding to the digital codes of 0 to 4096. Using an Opamp Pair
AD7934-6
An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7934-6. The circuit configurations shown in Figure 32 and Figure 33 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. A suitable dual op amp that could be used in this configuration to provide differential drive to the AD7934-6 is the AD8022. Take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. The driver circuits in Figure 32 and Figure 33 are optimized for dc coupling applications requiring best distortion performance. The circuit configuration shown in Figure 32 converts a unipolar, single-ended signal into a differential signal. The circuit configuration in Figure 33 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the VREF level of the ADC.
Figure 30. Input Common Mode Range versus VREF (VDD=5V and VREF (max) = 3.5V)
Figure 31. Input Common Mode Range versus VREF (VDD=3V and VREF (max)=2.2V)
Driving Differential Inputs Differential operation requires that VIN+ and VIN- be simultaneously driven with two equal signals that are 180 out of phase. The common mode must be set up externally and has a range which is determined by VREF, the power supply and the particular amplifier used to drive the analog inputs. Differential modes of operation with either an ac or dc input, provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single ended to differential conversion.
Figure 32. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal
Figure 33. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Signal
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AD7934-6
Pseudo Differential Mode The AD7934-6 can have 2 Pseudo Differential pairs by setting the MODE0 and MODE1 bits in the control register to 1, 0 respectively. VIN+ is connected to the signal source which must have an amplitude of VREF to make use of the full dynamic range of the part. A DC input is applied to the VIN- pin. The voltage applied to this input provides an offset from ground or a pseudo ground for the VIN+ input. The benefit of pseudo differential inputs is that they separate the analog input signal ground from the ADC's ground allowing DC common mode voltages to be cancelled. Figure 34 shows a connection diagram for Pseudo Differential Mode.
Preliminary Technical Data
Figure 35. Normal Multichannel Operation Flow Chart
Using the Sequencer Consecutive Sequence (SEQ0 =1, SEQ1 = 1) A sequence of consecutive channels can be converted on beginning with channel 0 and ending with a final channel selected by writing to the ADD1 and ADD0 bits in the Control register. This is done by setting the SEQ0 and SEQ1 bits in the control register both to 1. Once the control register has been written to to set this mode up, the next conversion will be on Channel 0, then Channel 1 and so on until the channel selected by the address bits (ADD1 and ADD0) is reached. The ADC will then return to channel 0 and start the sequence again. The WR input must be kept high to ensure that the Control register is no accidentally overwritten and the sequence interrupted. This pattern will continue until such time as the AD7934-6 is written to. Figure 36 shows the flow chart of the Consecutive Sequence mode.
Figure 34. Pseudo Differential Mode Connection Diagram
ANALOG INPUT SELECTION
As shown in Table 7, the user can set up their analog input configuration by setting the values in the MODE0 and MODE1 bits in the Control Register. Assuming the configuration has been chosen, there are two different ways of selecting the analog input to be converted on depending on the state of the SEQ0 and SEQ1 bits in the Control register. Normal Multichannel Operation (SEQ0=SEQ1= 0) Any one of four analog input channels or 2 pairs of channels may be selected for conversion in any order by setting the SEQ0 & SEQ1 bits in the Control register both to 0. The channel to be converted on is selected by writing to the address bits ADD1 and ADD0 in the Control register to program the multiplexer prior to the conversion. This mode of operation is of a normal multichannel ADC where each data write selects the next channel for conversion. Figure 35 shows a flow chart of this mode of operation. The channel configurations are shown in Table 7.
Figure 36. Consecutive Sequence Mode Flow Chart
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Preliminary Technical Data
REFERENCE SECTION
The AD7934-6 can operate with either the on chip reference or an external reference. The internal reference is selected by setting the REF bit in the internal Control register to 1. A block diagram of the internal reference circuitry is shown in Figure 37. The internal reference circuitry includes an on-chip 2.5 V band gap reference, and a reference buffer. When using the internal reference the VREFIN/VREFOUT pin should be decoupled to AGND with a 0.47F capacitor. This internal reference not only provides the reference for the analog to digital conversion but can also be used externally in the system. It is recommended that the reference output is buffered using an external precision opamp before applying it anywhere in the system.
AD7934-6
Therefore, when operating at VDD = 5 V, the value of VREF can range from 100mV to a maximum value of 3.5V. When VDD = 4.75 V, VREF max = 3.17 V. Example 2: VINmax = VDD + 0.3 VINmax = VREF + VREF/2 If VDD = 3.6V then VINmax = 3.9 V Therefore 3xVREF/2 = 3.6 V VREF max = 2.6 V
Therefore, when operating with at VDD = 3 V, the value of VREF can range from 100mV to a maximum value of 2.4V. When VDD = 2.35 V, VREF max = 1.76 V. The above calculations assume that VCM = VREF. For lower common mode voltages, higher references may be applied. The user must just ensure that the maximum input signal is not greater than VDD = 0.3 V or less than 0 V - 0.3 V. These examples show that the maximum reference applied to the AD7934-6 is directly dependant on the value applied to VDD. The performance of the part at different reference values is shown in Figures TBD to TBD. The value of the reference sets the analog input span and the common mode voltage range. Errors in the reference source will result in gain errors in the AD7934-6 transfer function and will add to specified full scale errors on the part. Table 9 lists examples of suitable voltage references that could be used that are available from Analog Devices and Figure 38 shows a typical connection diagram for an external reference. Table 9. Examples of Suitable Voltage References
Reference Output Voltage 2.5/3 2.5 2.048 Initial Accuracy (% max) 0.04 0.04 0.05 Operating Current (A) 1000 500 500
Figure 37. Internal Reference Circuit Block Diagram
Alternatively, an external reference can be applied to the VREFIN/VREFOUT pin of the AD7934-6. An external reference input is selected by setting the REF bit in the internal Control register to 0. When using an external reference, the VREFIN/VREFOUT pin should be decoupled to AGND with a 0.1F capacitor. When operating in Differential mode, the external reference input range is 0.1 V to 3.5V and in Single ended and pseudo differential mode, the external reference input range is 0.1V to VDD. The specified reference is 2.5 V for VDD = 2.7 V to 5.25 V and VDD for VDD < 2.7 V. It is important to ensure that, when chosing the reference value, the maximum analog input range (VINmax) is never greater than VDD + 0.3V to comply with the maximum ratings of the device. In Pseudo Differential Mode, the user must ensure that VREFIN - VIN- VDD. The following two examples calculate the maximum VREF input that can be used when operating the AD7934-6 in Differential mode with a VDD of 5 V and 3 V respectively. Example 1: VINmax = VDD + 0.3 VINmax = VREF + VREF/2 If VDD = 5 V then VINmax = 5.3 V Therefore 3xVREF/2 = 5.3 V VREF max = 3.5 V
AD780 ADR421 ADR420
Figure 38. Typical VREF Connection Program
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AD7934-6
Digital Inputs The digital inputs applied to the AD7934-6 are not limited by the maximum ratings which limit the analog inputs. Instead, the digital inputs applied can go to 7V and are not restricted by the AVDD +0.3V limit as on the analog inputs. Another advantage of the digital inputs not being restricted by the AVDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If any of these inputs are applied before AVDD then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to AVDD. VDRIVE Input The AD7934-6 has a VDRIVE feature. VDRIVE controls the voltage at which the Parallel Interface operates. VDRIVE allows the ADC to easily interface to 1.8V, 3 V and 5 V processors. VDRIVE of 1.8 V can only be used if VDD = 2.35 V to 3.6 V. An example is, if the AD7934-6 was operated with an AVDD of 5V, and the VDRIVE pin could be powered from a 3V supply, the AD7934-6 has better dynamic performance with an AVDD of 5V while still being able to interface to 3V processors. Care should be taken to ensure VDRIVE does not exceed AVDD by more than 0.3 V. (See Absolute Maximum Ratings Section).
Preliminary Technical Data
With the W/B pin tied logic high, the AD7934-6 interface operates in Word mode. In this case, a single read operation from the device accesses the Conversion data word on pins DB0 to DB11. The DB8/HBEN pin assumes its DB8 function. With the W/B pin tied to logic low, the AD7934-6 interface operates in Byte mode. In this case, the DB8/HBEN pin assumes its HBEN function. Conversion data from the AD7934-6 must be accessed in two read operations with 8 bits of data provided on DB0 to DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low byte of the 12-bit word. For a low byte read, DB0 to DB7 provide the 8 LSBs of the 12-bit word. For a high byte read, DB0 to DB3 provide the 4MSBs of the 12-bit word. DB4 of the high byte is always zero and DB5 and DB6 of the high byte provide the Channel ID. Figure 4 shows the read cycle timing diagram for a 12-bit transfer. When operated in Word mode, the HBEN input does not exist and only the first read operation is required to access data from the device. When operated in Byte mode, the two read cycles shown in Figure 5 are required to access the full data word from the device. The CS and RD signals are gated internally and level triggered active low. In either Word mode or Byte mode, CS and RD may be tied together as the timing specification t10 and t11 is 0ns min. The data is placed onto the data bus a time t13 after both CS and RD go low. The RD rising edge can be used to latch data out of the device. After a time, t14, the data lines will become threestated. Alternatively, CS and RD can be tied permanently low and the conversion data will be valid and placed onto the data bus a time t9 before the falling edge of BUSY. Writing Data to the AD7934-6 With W/B tied logic high, a single Write operation transfers the full data word on DB0 to DB11 to the Control Register on the AD7934-6. The DB8/HBEN pin assumes its DB8 function. Data to be written to the AD7934-6 should be provided on the DB0 to DB11 inputs with DB0 being the LSB of the data word. With W/B tied logic low, the AD7934-6 requires two write operations to transfer a full 12-Bit word. DB8/HBEN assumes its HBEN function. Data to be written to the AD7934-6 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte which is to be written is high byte or low byte data. The low byte of the data word has DB0 being the LSB of the full data word. For the high byte write, HBEN should be high and the data on the DB0 input should be data bit 8 of the 12-bit word. Figure 2 shows the write cycle timing diagram of the AD7934-6. When operated in Word mode, the HBEN input does not exist and only the one write operation is required to write the word of data to the device. Data should be provided on DB0 to DB11. When operated in Byte mode, the two write cycles shown in
PARALLEL INTERFACE
The AD7934-6 has a flexible, parallel interface. This interface is 12-bits wide and is capable of operating in either Word (W/B tied high) or Byte (W/B tied low) mode. The CONVST signal is used to initiate conversions and when operating in Auto Shutdown or Auto Standby mode, it is used to power up the ADC. A falling edge on the CONVST signal is used to initiate conversions and it also puts the ADC track and hold into track. Once the CONVST signal goes low, the BUSY signal goes high for the duration of the Conversion. In between conversions, CONVST must be brought high for a minimum time of t1. This must happen after the 14th rising edge of CLKIN otherwise the conversion will be aborted and the track and hold will go back into track. At the end of the Conversion, BUSY goes low and can be used to activate an Interrupt Service Routine. The CS and RD lines are then activated in parallel to read the 12-bits of conversion data. When power supplies are first applied to the device, a rising edge on CONVST puts the track and hold into track. The acquisition time must be allowed before CONVST is brought low to initiate a conversion. The ADC will then go into hold on the falling edge of CONVST and back into track on the 13th rising edge of CLKIN after this. See Figure 4. When operating the device in Auto Shutdown or Auto Standby mode, where the ADC powers down at the end of each conversion, a rising edge on the CONVST signal is used to power up the device. Reading Data from the AD7934-6
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Preliminary Technical Data
Figure 3 are required to write the full data word to the AD79346. In Figure 3 the first write transfers the lower 8 bits of the data word from DB0 to DB7 and the second write transfers the upper 4 bits of the data word. When writing to the AD7934-6, the top 4 bits in the high byte must be 0s. The CS and WR signals are gated internally. CS and WR may be tied together as the timing specification for t4 and t5 is 0ns min. The data is latched into the device on the rising edge of WR. The data needs to be setup a time t7 before the WR rising edge and held for a time t8 after the WR rising edge.
AD7934-6
powered down. The part retains the information in the Control Register during the Full Shutdown. The AD7934-6 remains in Full Shutdown mode until the power management bits (PM1 and PM0) in the Control Register are changed. If a write to the Control register occurs while the part is in Full Shutdown mode, and the Power Management bits are changed to PM0 = PM1 = 0, i.e. Normal Mode, the part will begin to power up on the CONVST rising edge. To ensure the part is fully powered up before a conversion is initiated, the power up time, TBD, should be allowed before the CONVST falling edge, otherwise, invalid data will be read.
POWER VS. THROUGHPUT RATE
A big advantage of powering the ADC down after a conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the different power modes, the AD7934-6 is only powered up for the duration of the conversion. Therefore, the average power consumption per cycle is significantly reduced. Figure 39 and Figure 40 show plots of power vs. throughput when operating in Auto shutdown and Auto Standby modes.
POWER MODES OF OPERATION
The AD7934-6 has four different power modes of operation. These modes are designed to provide flexible power management options. Different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. The mode of operation is selected by the power management bits, PM1 and PM0, in the Control register, as detailed in Table 6. At power on reset, the default power up condition is Normal Mode. Normal Mode (PM1 = PM0 = 0) This mode is intended for the fastest throughput rate performance as the user does not have to worry about any power up times as the AD7934-6 remains fully powered up at all times. At power on reset, this mode is the default setting in the control register. AutoShutdown (PM1 = 0; PM0 = 1) In this mode of operation, the AD7934-6 automatically enters full shutdown at the end of each conversion which is shown at point A in Figure 4. In shutdown mode, all internal circuitry on the device is powered down. The part retains information in the Control register during shutdown. It remains in shutdown mode until the next rising edge of CONVST (see point B in Figure 4). On this rising edge, the part will begin to power up and the power up time will depend on whether the user is operating with the internal or external reference. With the internal reference, the power up time is typically TBD and with an external reference, the power up time is typically TBD. The user should ensure that the power up time has elapsed before initiating a conversion. Auto Standby (PM1 = 1; PM0 = 0) In this mode of operation, the AD7934-6 automatically enters Standby mode at the end of each conversion. When this mode is entered, all circuitry on the AD7934-6 is partially powered down. A rising edge on CONVST will power up the device which will take at least TBD. Full Shutdown Mode (PM1 =1; PM0 = 1) When this mode is entered, all circuitry on the AD7934-6 is
Figure 39. Power vs. Throughput in Auto Shutdown Mode
Figure 40. Power vs. Throughput in Auto Standby Mode.
MICROPROCESSOR INTERFACING
AD7934-6 To ADSP-21xx Interface Figure 41 shows the AD7934-6 interfaced to the ADSP-21xx series of DSPs as a memory mapped device. A single wait state may be necessary to interface the AD7934-6 to the ADSP-21xx depending on the clock speed of the DSP. The wait state can be programmed via the Data Memory Wait state Control Register of the ADSP-21xx (please see the ADSP-21xx family Users
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AD7934-6
Manual for details). The following instruction reads from the AD7934-6: MR = DM(ADC) Where ADC is the address of the AD7934-6.
Preliminary Technical Data
If high speed glue logic such as 74AS devices are used to drive the RD and the WR lines when interfacing to the TMS320C25, then again, no wait states are necessary. However, if slower logic is used, data accesses may be slowed sufficiently when reading from and writing to the part to require the insertion of one wait state. Extra wait states will be necessary when using the TMS320C5x at their fastest clock speeds. (please see the TMS320C5x User Guide for details). Data is read from the ADC using the following instruction: IN D, ADC Where D is Data Memory address and the ADC is the AD79346 address.
Figure 41. Interfacing to the ADSP-21xx
AD7934-6 To ADSP-21065 Interface Figure 42 shows a typical interface between the AD7934-6 and the ADSP-21065L SHARC processor. This interface is an example of one of three DMA handshake modes. The MSx control line is actually three memory select lines. Internal ADDR25-24 are decoded into MS3-0, these lines are then asserted as chip selects. The DMAR1 (DMA request 1) is used in this setup as the interrupt to signal end of conversion. The rest of the interface is standard handshaking operation.
Figure 43. Interfacing to the TMS32020/C25/C5x
AD7934-6 to 80C186 Interface Figure 44 shows the AD7934-6 interfaced to the 80C186 microprocessor. The 80C186 DMA controller provides two independent high speed DMA channels where data transfer can occur between memory and I/O spaces. Each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. After the AD7934-6 has finished a conversion, the BUSY line generates a DMA request to Channel 1 (DRQ1). As a result of the interrupt, the processor performs a DMA READ operation which also resets the interrupt latch. Sufficient priority must be assigned to the DMA channel to ensure that the DMA request will be serviced before the completion of the next conversion.
Figure 42. Interfacing to the ADSP-21065L
AD7934-6 To TMS32020, TMS320C25 and TMS320C5x Interface The parallel interface between the AD7934-6 and the TMS32020, TMS320C25 and TMS320C5x family of DSPs are shown in Figure 43. The memory mapped address chosen for the AD7934-6 should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7934-6 is fast enough to interface to the TMS32020 with no extra wait states.
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Preliminary Technical Data
Figure 44. Interfacing to the 80C186
AD7934-6
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AD7934-6
APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7934-6 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place and the connection should be a star ground point established as close to the Ground pins on the AD7934-6 as possible. Avoid running digital lines under the device as this will couple noise onto the die. The analog ground plane should be allowed to run under the AD7934-6 to avoid noise coupling. The power supply lines to the AD7934-6 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital
Preliminary Technical Data
ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a doublesided board. In this technique the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10F tantalum capacitors in parallel with 0.1F capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device.
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Preliminary Technical Data OUTLINE DIMENSIONS
AD7934-6
Figure 45. 28 Lead TSSOP Package Dimensions Dimensions shown in inches and mm
ORDERING GUIDE
Model AD7934-6BRU EVAL-ADxxxxCB2 EVAL-CONTROL BRD23 Range -40C to +85C Evaluation Board Controller Board Linearity Error (LSB)1 1 Package Option RU-32 Package Descriptions TSSOP
1 2 3
Linearity error here refers to integral linearity error. This can be used as a stand-alone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (EVALADxxxxCB), the EVAL-CONTROL BRD2 and a 12 V ac transformer. See the ADxxxx evaluation board technical note for more details.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. PR04752-0-3/04(PrB) Printed in the U.S.A.
Rev. PrB | Page 27 of 27
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